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sv: support assignments within expressions #3920

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merged 3 commits into from
Sep 20, 2023
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@zachjs zachjs commented Sep 6, 2023

  • Add support for assignments within expressions, e.g., x[y++] = z; or x = (y *= 2) - 1;. The logic is handled entirely within the parser by injecting statements into the current procedural block.
  • Add support for pre-increment/decrement statements, which are behaviorally equivalent to post-increment/decrement statements.
  • Fix non-standard attribute position used for post-increment/decrement statements.

I am not particularly attached to this implementation. I had initially anticipated adding a new AST node type and elaborating them in simplify.cc, but sticking the statements into the current procedure ended up working quite naturally.

Closes #3870.

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.
// The position 1 attr to avoid shift/reduce conflicts with the
// other productions. We reject attributes in that position.
if (!$1->empty())
frontend_verilog_yyerror("Attributes are not allowed on this size of the lvalue in an inc_or_dec_expression!");
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As far as I can tell these attributes would be allowed by the standard, since attributes can be prefix to a statement and this is a self-standing statement, no?

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Good point! I'll pushing a fix for this shortly.


// create a pre/post-increment/decrement expression, and add the corresponding statement
static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo)
{
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I think we want to recover the sizing information here, or do something other than the plus one minus one dance (maybe an assignment to a dummy wire?). Consider the following:

  w = {1, r++};

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This is a great catch! I should have set the width of minus_one explicitly to prevent it from affecting the width of the expression. This logic seems simpler than the alternatives I considered: A) adding a temporary wire; or B) actually doing the increment afterwards. That said, my preference here likely comes from having done it the same way in sv2v.

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povik commented Sep 18, 2023

Other than the two comments I went through all of it and it looks good.

@zachjs zachjs requested a review from povik September 19, 2023 03:47
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Looking good!

@povik povik merged commit 99a5773 into YosysHQ:master Sep 20, 2023
@zachjs zachjs deleted the asgn-expr branch September 22, 2023 01:19
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SystemVerilog procedural assignments within expressions
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